The core manages ARP replies and requests autonomously with configurable expiration time of the retrieved MAC-IP address association and automatic renewing. In a similar way, a Unified Packet Composer encapsulates the user provided UDP payload into UDP, IP and Ethernet. In addition, the parser implements user defined packet filters. A single optimised parser handles Ethernet, IP and UDP protocols with minimal latency and resources utilisation. The RX path consists of a Unified Parser that can be configured to support a wide range of data path width and clock frequency. The user can select different destination IP addresses using the TDEST field. A simple user interface based on the AXI4-Stream protocol transfer UDP payload data to/from the IP core. The 10/40 G UDP Sybsystem is based on a scalable architecture supporting different Ethernet protocols. The IP core block diagram is shown below : The IP core implements the UDP/IP part (bolded fields) of the communication stack represented in the following table. _(*) Actual resource utilization depends on selected speed and timing parameters_ CRC check/generation for incoming/outgoing Ethernet packets.Supports broadcast TX/RX Ethernet and IP packets.ARP table with programmable entries number.10 Gbit/s or 40Gbit/s transfer rate over Ethernet.VHDL Test-bench, optional BIST, test application The 40/10 Gb Ethernet Controller has assigned programmable MAC and IP addresses. It provides a standard AXI4 interface for user applications The controller implements the UDP protocol over a LAN (Local Area Network). The core provides an effective infrastructure to implement very high-speed communication between an FPGA and one or several network devices, providing up to 40Gbit/s transfer rate over Ethernet.

10g mac ethernet project